Dynamic load balancing of compute assets among different compute contexts

ABSTRACT

Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/339,184, filed Jun. 4, 2021, which is a continuation of U.S. patentapplication Ser. No. 16/367,056, filed Mar. 27, 2019. The entirespecifications of which are hereby incorporated herein by reference intheir entirety.

FIELD

Embodiments generally to the field of graphics processors and workloadexecution.

RELATED ART

Digital image generation, processing, and display are widely performedand employed by computing systems and computer-executed applications.For example, smart phones, smart homes, security systems, self-drivingvehicles, and computer gaming applications generate digital images oremploy image processing. In some cases, two dimensional (2D) or threedimensional (3D) images are generated and displayed by a computersystem.

A processing device can be programmed to handle workloads from varioussources. However, in some cases of allocating the processing device tohandle workloads from various sources, the processing device can beunder-utilized. For example, in a time-sliced use of a graphicsprocessing unit (GPU), a GPU can be allocated to process contexts from asingle application at a time. If a second application requests to submitcontexts for processing to the GPU, the second application must wait forin-process threads from the first application to complete, even if theGPU has spare capacity to handle threads from the second application.Context and resulting data from the first application's use of the GPUare cleared from memory before a context from the second application canuse the GPU. In other words, a single application and single context canuse GPU at a time.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIG. 1 is a block diagram of an embodiment of a computer system with aprocessor having one or more processor cores and graphics processors;

FIG. 2 is a block diagram of one embodiment of a processor having one ormore processor cores, an integrated memory controller, and an integratedgraphics processor;

FIG. 3 is a block diagram of one embodiment of a graphics processorwhich may be a discreet graphics processing unit, or may be graphicsprocessor integrated with a plurality of processing cores;

FIG. 4 is a block diagram of an embodiment of a graphics-processingengine for a graphics processor;

FIG. 5 is a block diagram of another embodiment of a graphics processor;

FIGS. 6A and 6B are block diagrams of thread execution logic includingan array of processing elements;

FIG. 7 illustrates a graphics processor execution unit instructionformat according to an embodiment;

FIG. 8 is a block diagram of another embodiment of a graphics processorwhich includes a graphics pipeline, a media pipeline, a display engine,thread execution logic, and a render output pipeline;

FIG. 9A is a block diagram illustrating a graphics processor commandformat according to an embodiment;

FIG. 9B is a block diagram illustrating a graphics processor commandsequence according to an embodiment;

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to an embodiment;

FIGS. 11A and 11B illustrate exemplary IP core development systems thatmay be used to manufacture an integrated circuit to perform operationsaccording to an embodiment;

FIG. 12 illustrates an exemplary system on a chip integrated circuitthat may be fabricated using one or more IP cores, according to anembodiment;

FIGS. 13A and 13B illustrate an exemplary graphics processor of a systemon a chip integrated circuit that may be fabricated using one or more IPcores;

FIGS. 14A and 14B illustrate an additional exemplary graphics processorof a system on a chip integrated circuit that may be fabricated usingone or more IP cores;

FIG. 15 depicts an example environment;

FIG. 16 depicts an example process;

FIG. 17A depicts an example graphics processing unit system;

FIG. 17B depicts an example global compute front end;

FIG. 18 depicts an example of distribution of work;

FIG. 19 depicts an example use of thread execution;

FIG. 20 depicts an example resource allocation scheme;

FIG. 21 depicts an example of movement between states;

FIG. 22 depicts an example of time taken for processing contexts; and

FIG. 23 depicts an example process.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

EXEMPLARY GRAPHICS PROCESSOR ARCHITECTURES AND DATA TYPES SystemOverview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. System 100 may be used in a single processor desktop system,a multiprocessor workstation system, or a server system having a largenumber of processors 102 or processor cores 107. In one embodiment, thesystem 100 is a processing platform incorporated within asystem-on-a-chip (SoC) integrated circuit for use in mobile, handheld,or embedded devices such as within Internet-of-things (IoT) devices withwired or wireless connectivity to a local or wide area network.

In one embodiment, system 100 can include, couple with, or be integratedwithin: a server-based gaming platform; a game console, including a gameand media console; a mobile gaming console, a handheld game console, oran online game console. In some embodiments the system 100 is part of amobile phone, smart phone, tablet computing device or mobileInternet-connected device such as a laptop with low internal storagecapacity. Processing system 100 can also include, couple with, or beintegrated within: a wearable device, such as a smart watch wearabledevice; smart eyewear or clothing enhanced with augmented reality (AR)or virtual reality (VR) features to provide visual, audio or tactileoutputs to supplement real world visual, audio or tactile experiences orotherwise provide text, audio, graphics, video, holographic images orvideo, or tactile feedback; other augmented reality (AR) device; orother virtual reality (VR) device. In some embodiments, the processingsystem 100 includes or is part of a television or set top box device.

In an embodiment, system 100 can include, couple with, or be integratedwithin a self-driving vehicle such as a bus, tractor trailer, car, motoror electric power cycle, plane or glider (or any combination thereof).The self-driving vehicle may use system 100 to process the environmentsensed around the vehicle.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system or user software. In some embodiments, atleast one of the one or more processor cores 107 is configured toprocess a specific instruction set 109. In some embodiments, instructionset 109 may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). One or more processor cores 107 may process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such as a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 can be additionallyincluded in processor 102 and may include different types of registersfor storing different types of data (e.g., integer registers, floatingpoint registers, status registers, and an instruction pointer register).Some registers may be general-purpose registers, while other registersmay be specific to the design of the processor 102.

In some embodiments, one or more processor(s) 102 are coupled with oneor more interface bus(es) 110 to transmit communication signals such asaddress, data, or control signals between processor 102 and othercomponents in the system 100. The interface bus 110, in one embodiment,can be a processor bus, such as a version of the Direct Media Interface(DMI) bus. However, processor busses are not limited to the DMI bus, andmay include one or more Peripheral Component Interconnect buses (e.g.,PCI, PCI Express), memory busses, or other types of interface busses. Inone embodiment the processor(s) 102 include an integrated memorycontroller 116 and a platform controller hub 130. The memory controller116 facilitates communication between a memory device and othercomponents of the system 100, while the platform controller hub (PCH)130 provides connections to I/O devices via a local I/O bus.

The memory device 120 can be a dynamic random access memory (DRAM)device, a static random access memory (SRAM) device, flash memorydevice, phase-change memory device, or some other memory device havingsuitable performance to serve as process memory. In one embodiment thememory device 120 can operate as system memory for the system 100, tostore data 122 and instructions 121 for use when the one or moreprocessors 102 executes an application or process. Memory controller 116also couples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations. In some embodiments adisplay device 111 can connect to the processor(s) 102. The displaydevice 111 can be one or more of an internal display device, as in amobile electronic device or a laptop device or an external displaydevice attached via a display interface (e.g., DisplayPort, etc.). Inone embodiment the display device 111 can be a head mounted display(HMD) such as a stereoscopic display device for use in virtual reality(VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub 130 enables peripheralsto connect to memory device 120 and processor 102 via a high-speed I/Obus. The I/O peripherals include, but are not limited to, an audiocontroller 146, a network controller 134, a firmware interface 128, awireless transceiver 126, touch sensors 125, a data storage device 124(e.g., non-volatile memory, volatile memory, hard disk drive, flashmemory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). The touch sensors 125 can include touch screen sensors,pressure sensors, or fingerprint sensors. The wireless transceiver 126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile networktransceiver such as a 3G, 4G, 5G, or Long Term Evolution (LTE)transceiver. The firmware interface 128 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). The network controller 134 can enable a networkconnection to a wired network. In some embodiments, a high-performancenetwork controller (not shown) couples with the interface bus 110. Theaudio controller 146, in one embodiment, is a multi-channel highdefinition audio controller. In one embodiment the system 100 includesan optional legacy I/O controller 140 for coupling legacy (e.g.,Personal System 2 (PS/2)) devices to the system. The platform controllerhub 130 can also connect to one or more Universal Serial Bus (USB)controllers 142 connect input devices, such as keyboard and mouse 143combinations, a camera 144, or other USB input devices.

It will be appreciated that the system 100 shown is exemplary and notlimiting, as other types of data processing systems that are differentlyconfigured may also be used. For example, an instance of the memorycontroller 116 and platform controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112. In one embodiment the platform controller hub 130 and/ormemory controller 116 may be external to the one or more processor(s)102. For example, the system 100 can include an external memorycontroller 116 and platform controller hub 130, which may be configuredas a memory controller hub and peripheral controller hub within a systemchipset that is in communication with the processor(s) 102.

For example, circuit boards (“sleds”) can be used on which componentssuch as CPUs, memory, and other components are placed are designed forincreased thermal performance. In some examples, processing componentssuch as the processors are located on a top side of a sled while nearmemory, such as DIMMs, are located on a bottom side of the sled. As aresult of the enhanced airflow provided by this design, the componentsmay operate at higher frequencies and power levels than in typicalsystems, thereby increasing performance. Furthermore, the sleds areconfigured to blindly mate with power and data communication cables in arack, thereby enhancing their ability to be quickly removed, upgraded,reinstalled, and/or replaced. Similarly, individual components locatedon the sleds, such as processors, accelerators, memory, and data storagedrives, are configured to be easily upgraded due to their increasedspacing from each other. In the illustrative embodiment, the componentsadditionally include hardware attestation features to prove theirauthenticity.

A data center can utilize a single network architecture (“fabric”) thatsupports multiple other network architectures including Ethernet andOmni-Path. The sleds can be coupled to switches via optical fibers,which provide higher bandwidth and lower latency than typical twistedpair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due tothe high bandwidth, low latency interconnections and networkarchitecture, the data center may, in use, pool resources, such asmemory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs,neural network and/or artificial intelligence accelerators, etc.), anddata storage drives that are physically disaggregated, and provide themto compute resources (e.g., processors) on an as needed basis, enablingthe compute resources to access the pooled resources as if they werelocal.

A power supply or source can provide voltage and/or current to system100 or any component or system described herein. In one example, thepower supply includes an AC to DC (alternating current to directcurrent) adapter to plug into a wall outlet. Such AC power can berenewable energy (e.g., solar power) power source. In one example, powersource includes a DC power source, such as an external AC to DCconverter. In one example, power source or power supply includeswireless charging hardware to charge via proximity to a charging field.In one example, power source can include an internal battery,alternating current supply, motion-based power supply, solar powersupply, or fuel cell source.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more PCI or PCI express busses. System agent core 210 providesmanagement functionality for the various processor components. In someembodiments, system agent core 210 includes one or more integratedmemory controllers 214 to manage access to various external memorydevices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, the systemagent core 210 also includes a display controller 211 to drive graphicsprocessor output to one or more coupled displays. In some embodiments,display controller 211 may also be a separate module coupled with thegraphics processor via at least one interconnect, or may be integratedwithin the graphics processor 208.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 can use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment, processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. In one embodiment,processor cores 202A-202N are heterogeneous in terms of computationalcapability. Additionally, processor 200 can be implemented on one ormore chips or as an SoC integrated circuit having the illustratedcomponents, in addition to other components.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores, or other semiconductordevices such as, but not limited to, memory devices or networkinterfaces. In some embodiments, the graphics processor communicates viaa memory mapped I/O interface to registers on the graphics processor andwith commands placed into the processor memory. In some embodiments,graphics processor 300 includes a memory interface 314 to access memory.Memory interface 314 can be an interface to local memory, one or moreinternal caches, one or more shared external caches, and/or to systemmemory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. The display device 320 can be an internal orexternal display device. In one embodiment the display device 320 is ahead mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In some embodiments,graphics processor 300 includes a video codec engine 306 to encode,decode, or transcode media to, from, or between one or more mediaencoding formats, including, but not limited to Moving Picture ExpertsGroup (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formatssuch as H.264/MPEG-4 AVC, H.265/HEVC, Alliance for Open Media (AOMedia)VP8, VP9, as well as the Society of Motion Picture & TelevisionEngineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG)formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3 . Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3 are illustrated. The media pipeline 316is optional in some embodiments of the GPE 410 and may not be explicitlyincluded within the GPE 410. For example and in at least one embodiment,a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414. In one embodiment thegraphics core array 414 include one or more blocks of graphics cores(e.g., graphics core(s) 415A, graphics core(s) 415B), each blockincluding one or more graphics cores. Each graphics core includes a setof graphics execution resources that includes general-purpose andgraphics specific execution logic to perform graphics and computeoperations, as well as fixed function texture processing and/or machinelearning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline 312 can include fixed functionand programmable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing theinstructions and dispatching execution threads to the graphics corearray 414. The graphics core array 414 provides a unified block ofexecution resources for use in processing these shader programs.Multi-purpose execution logic (e.g., execution units) within thegraphics core(s) 415A-414B of the graphic core array 414 includessupport for various 3D API shader languages and can execute multiplesimultaneous execution threads associated with multiple shaders.

In some embodiments, the graphics core array 414 includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units include general-purpose logicthat is programmable to perform parallel general-purpose computationaloperations, in addition to graphics processing operations. Thegeneral-purpose logic can perform processing operations in parallel orin conjunction with general-purpose logic within the processor core(s)107 of FIG. 1 or core 202A-202N as in FIG. 2 .

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420.

A shared function is implemented at least in a case where the demand fora given specialized function is insufficient for inclusion within thegraphics core array 414. Instead a single instantiation of thatspecialized function is implemented as a stand-alone entity in theshared function logic 420 and shared among the execution resourceswithin the graphics core array 414. The precise set of functions thatare shared between the graphics core array 414 and included within thegraphics core array 414 varies across embodiments. In some embodiments,specific shared functions within the shared function logic 420 that areused extensively by the graphics core array 414 may be included withinshared function logic 416 within the graphics core array 414. In variousembodiments, the shared function logic 416 within the graphics corearray 414 can include some or all logic within the shared function logic420. In one embodiment, all logic elements within the shared functionlogic 420 may be duplicated within the shared function logic 416 of thegraphics core array 414. In one embodiment the shared function logic 420is excluded in favor of the shared function logic 416 within thegraphics core array 414.

FIG. 5 is a block diagram of hardware logic of a graphics processor core500, according to some embodiments described herein. Elements of FIG. 5having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Theillustrated graphics processor core 500, in some embodiments, isincluded within the graphics core array 414 of FIG. 4 . The graphicsprocessor core 500, sometimes referred to as a core slice, can be one ormultiple graphics cores within a modular graphics processor. Thegraphics processor core 500 is exemplary of one graphics core slice, anda graphics processor as described herein may include multiple graphicscore slices based on target power and performance envelopes. Eachgraphics processor core 500 can include a fixed function block 530coupled with multiple sub-cores 501A-501F, also referred to assub-slices, that include modular blocks of general-purpose and fixedfunction logic.

In some embodiments, the fixed function block 530 includes ageometry/fixed function pipeline 536 that can be shared by all sub-coresin the graphics processor core 500, for example, in lower performanceand/or lower power graphics processor implementations. In variousembodiments, the geometry/fixed function pipeline 536 includes a 3Dfixed function pipeline (e.g., 3D pipeline 312 as in FIG. 3 and FIG. 4 )a video front-end unit, a thread spawner and thread dispatcher, and aunified return buffer manager, which manages unified return buffers,such as the unified return buffer 418 of FIG. 4 .

In one embodiment the fixed function block 530 also includes a graphicsSoC interface 537, a graphics microcontroller 538, and a media pipeline539. The graphics SoC interface 537 provides an interface between thegraphics processor core 500 and other processor cores within a system ona chip integrated circuit. The graphics microcontroller 538 is aprogrammable sub-processor that is configurable to manage variousfunctions of the graphics processor core 500, including thread dispatch,scheduling, and pre-emption. The media pipeline 539 (e.g., mediapipeline 316 of FIG. 3 and FIG. 4 ) includes logic to facilitate thedecoding, encoding, pre-processing, and/or post-processing of multimediadata, including image and video data. The media pipeline 539 implementmedia operations via requests to compute or sampling logic within thesub-cores 501-501F.

In one embodiment the SoC interface 537 enables the graphics processorcore 500 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared last level cache memory, the systemRAM, and/or embedded on-chip or on-package DRAM. The SoC interface 537can also enable communication with fixed function devices within theSoC, such as camera imaging pipelines, and enables the use of and/orimplements global memory atomics that may be shared between the graphicsprocessor core 500 and CPUs within the SoC. The SoC interface 537 canalso implement power management controls for the graphics processor core500 and enable an interface between a clock domain of the graphic core500 and other clock domains within the SoC. In one embodiment the SoCinterface 537 enables receipt of command buffers from a command streamerand global thread dispatcher that are configured to provide commands andinstructions to each of one or more graphics cores within a graphicsprocessor. The commands and instructions can be dispatched to the mediapipeline 539, when media operations are to be performed, or a geometryand fixed function pipeline (e.g., geometry and fixed function pipeline536, geometry and fixed function pipeline 514) when graphics processingoperations are to be performed.

The graphics microcontroller 538 can be configured to perform variousscheduling and management tasks for the graphics processor core 500. Inone embodiment the graphics microcontroller 538 can perform graphicsand/or compute workload scheduling on the various graphics parallelengines within execution unit (EU) arrays 502A-502F, 504A-504F withinthe sub-cores 501A-501F. In this scheduling model, host softwareexecuting on a CPU core of an SoC including the graphics processor core500 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on the appropriate graphics engine.Scheduling operations include determining which workload to run next,submitting a workload to a command streamer, pre-empting existingworkloads running on an engine, monitoring progress of a workload, andnotifying host software when a workload is complete. In one embodimentthe graphics microcontroller 538 can also facilitate low-power or idlestates for the graphics processor core 500, providing the graphicsprocessor core 500 with the ability to save and restore registers withinthe graphics processor core 500 across low-power state transitionsindependently from the operating system and/or graphics driver softwareon the system.

The graphics processor core 500 may have greater than or fewer than theillustrated sub-cores 501A-501F, up to N modular sub-cores. For each setof N sub-cores, the graphics processor core 500 can also include sharedfunction logic 510, shared and/or cache memory 512, a geometry/fixedfunction pipeline 514, as well as additional fixed function logic 516 toaccelerate various graphics and compute processing operations. Theshared function logic 510 can include logic units associated with theshared function logic 420 of FIG. 4 (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin the graphics processor core 500. The shared and/or cache memory512 can be a last-level cache for the set of N sub-cores 501A-501Fwithin the graphics processor core 500, and can also serve as sharedmemory that is accessible by multiple sub-cores. The geometry/fixedfunction pipeline 514 can be included instead of the geometry/fixedfunction pipeline 536 within the fixed function block 530 and caninclude the same or similar logic units.

In one embodiment the graphics processor core 500 includes additionalfixed function logic 516 that can include various fixed functionacceleration logic for use by the graphics processor core 500. In oneembodiment the additional fixed function logic 516 includes anadditional geometry pipeline for use in position only shading. Inposition-only shading, two geometry pipelines exist, the full geometrypipeline within the geometry/fixed function pipeline 516, 536, and acull pipeline, which is an additional geometry pipeline which may beincluded within the additional fixed function logic 516. In oneembodiment the cull pipeline is a trimmed down version of the fullgeometry pipeline. The full pipeline and the cull pipeline can executedifferent instances of the same application, each instance having aseparate context. Position only shading can hide long cull runs ofdiscarded triangles, enabling shading to be completed earlier in someinstances. For example and in one embodiment the cull pipeline logicwithin the additional fixed function logic 516 can execute positionshaders in parallel with the main application and generally generatescritical results faster than the full pipeline, as the cull pipelinefetches and shades only the position attribute of the vertices, withoutperforming rasterization and rendering of the pixels to the framebuffer. The cull pipeline can use the generated critical results tocompute visibility information for all the triangles without regard towhether those triangles are culled. The full pipeline (which in thisinstance may be referred to as a replay pipeline) can consume thevisibility information to skip the culled triangles to shade only thevisible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic 516 can alsoinclude machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

Within each graphics sub-core 501A-501F includes a set of executionresources that may be used to perform graphics, media, and computeoperations in response to requests by graphics pipeline, media pipeline,or shader programs. The graphics sub-cores 501A-501F include multiple EUarrays 502A-502F, 504A-504F, thread dispatch and inter-threadcommunication (TD/IC) logic 503A-503F, a 3D (e.g., texture) sampler505A-505F, a media sampler 506A-506F, a shader processor 507A-507F, andshared local memory (SLM) 508A-508F. The EU arrays 502A-502F, 504A-504Feach include multiple execution units, which are general-purposegraphics processing units capable of performing floating-point andinteger/fixed-point logic operations in service of a graphics, media, orcompute operation, including graphics, media, or compute shaderprograms. The TD/IC logic 503A-503F performs local thread dispatch andthread control operations for the execution units within a sub-core andfacilitate communication between threads executing on the executionunits of the sub-core. The 3D sampler 505A-505F can read texture orother 3D graphics related data into memory. The 3D sampler can readtexture data differently based on a configured sample state and thetexture format associated with a given texture. The media sampler506A-506F can perform similar read operations based on the type andformat associated with media data. In one embodiment, each graphicssub-core 501A-501F can alternately include a unified 3D and mediasampler. Threads executing on the execution units within each of thesub-cores 501A-501F can make use of shared local memory 508A-508F withineach sub-core, to enable threads executing within a thread group toexecute using a common pool of on-chip memory.

Execution Units

FIGS. 6A-6B illustrate thread execution logic 600 including an array ofprocessing elements employed in a graphics processor core according toembodiments described herein. Elements of FIGS. 6A-6B having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. FIG. 6A illustrates anoverview of thread execution logic 600, which can include a variant ofthe hardware logic illustrated with each sub-core 501A-501F of FIG. 5 .FIG. 6B illustrates exemplary internal details of an execution unit.

As illustrated in FIG. 6A, in some embodiments thread execution logic600 includes a shader processor 602, a thread dispatcher 604,instruction cache 606, a scalable execution unit array including aplurality of execution units 608A-608N, a sampler 610, a data cache 612,and a data port 614. In one embodiment the scalable execution unit arraycan dynamically scale by enabling or disabling one or more executionunits (e.g., any of execution unit 608A, 608B, 608C, 608D, through608N-1 and 608N) based on the computational requirements of a workload.In one embodiment the included components are interconnected via aninterconnect fabric that links to each of the components. In someembodiments, thread execution logic 600 includes one or more connectionsto memory, such as system memory or cache memory, through one or more ofinstruction cache 606, data port 614, sampler 610, and execution units608A-608N. In some embodiments, each execution unit (e.g. 608A) is astand-alone programmable general-purpose computational unit that iscapable of executing multiple simultaneous hardware threads whileprocessing multiple data elements in parallel for each thread. Invarious embodiments, the array of execution units 608A-608N is scalableto include any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, a geometry pipeline can dispatch vertex, tessellation, orgeometry shaders to the thread execution logic for processing. In someembodiments, thread dispatcher 604 can also process runtime threadspawning requests from the executing shader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader. Various embodimentscan apply to use execution by use of Single Instruction Multiple Thread(SIMT) as an alternate to use of SIMD or in addition to use of SIMD.Reference to a SIMD core or operation can apply also to SIMT or apply toSIMD in combination with SIMT.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into afused execution unit 609A-609N having thread control logic (607A-607N)that is common to the fused EUs. Multiple EUs can be fused into an EUgroup. Each EU in the fused EU group can be configured to execute aseparate SIMD hardware thread. The number of EUs in a fused EU group canvary according to embodiments. Additionally, various SIMD widths can beperformed per-EU, including but not limited to SIMD8, SIMD16, andSIMD32. Each fused graphics execution unit 609A-609N includes at leasttwo execution units. For example, fused execution unit 609A includes afirst EU 608A, second EU 608B, and thread control logic 607A that iscommon to the first EU 608A and the second EU 608B. The thread controllogic 607A controls threads executed on the fused graphics executionunit 609A, allowing each EU within the fused execution units 609A-609Nto execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, shader processor 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 to output processed data tomemory for further processing on a graphics processor output pipeline.In some embodiments, the data port 614 includes or couples to one ormore cache memories (e.g., data cache 612) to cache data for memoryaccess via the data port.

As illustrated in FIG. 6B, a graphics execution unit 608 can include aninstruction fetch unit 637, a general register file array (GRF) 624, anarchitectural register file array (ARF) 626, a thread arbiter 622, asend unit 630, a branch unit 632, a set of SIMD floating point units(FPUs) 634, and in one embodiment a set of dedicated integer SIMD ALUs635. The GRF 624 and ARF 626 includes the set of general register filesand architecture register files associated with each simultaneoushardware thread that may be active in the graphics execution unit 608.In one embodiment, per thread architectural state is maintained in theARF 626, while data used during thread execution is stored in the GRF624. The execution state of each thread, including the instructionpointers for each thread, can be held in thread-specific registers inthe ARF 626.

In one embodiment the graphics execution unit 608 has an architecturethat is a combination of Simultaneous Multi-Threading (SMT) andfine-grained Interleaved Multi-Threading (IMT). The architecture has amodular configuration that can be fine tuned at design time based on atarget number of simultaneous threads and number of registers perexecution unit, where execution unit resources are divided across logicused to execute multiple simultaneous threads.

In one embodiment, the graphics execution unit 608 can co-issue multipleinstructions, which may each be different instructions. The threadarbiter 622 of the graphics execution unit thread 608 can dispatch theinstructions to one of the send unit 630, branch unit 632, or SIMDFPU(s) 634 for execution. Each execution thread can access 128general-purpose registers within the GRF 624, where each register canstore 32 bytes, accessible as a SIMD 8-element vector of 32-bit dataelements. In one embodiment, each execution unit thread has access to 4Kbytes within the GRF 624, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In one embodiment up to seven threads can executesimultaneously, although the number of threads per execution unit canalso vary according to embodiments. In an embodiment in which seventhreads may access 4 Kbytes, the GRF 624 can store a total of 28 Kbytes.Flexible addressing modes can permit registers to be addressed togetherto build effectively wider registers or to represent strided rectangularblock data structures.

In one embodiment, memory operations, sampler operations, and otherlonger-latency system communications are dispatched via “send”instructions that are executed by the message passing send unit 630. Inone embodiment, branch instructions are dispatched to a dedicated branchunit 632 to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit 608 includes one or moreSIMD floating point units (FPU(s)) 634 to perform floating-pointoperations. In one embodiment, the FPU(s) 634 also support integercomputation. In one embodiment the FPU(s) 634 can SIMD execute up to Mnumber of 32-bit floating-point (or integer) operations, or SIMD executeup to 2M 16-bit integer or 16-bit floating-point operations. In oneembodiment, at least one of the FPU(s) provides extended math capabilityto support high-throughput transcendental math functions and doubleprecision 64-bit floating-point. In some embodiments, a set of 8-bitinteger SIMD ALUs 635 are also present, and may be specificallyoptimized to perform operations associated with machine learningcomputations.

In one embodiment, arrays of multiple instances of the graphicsexecution unit 608 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). For scalability, product architects can choose theexact number of execution units per sub-core grouping. In one embodimentthe execution unit 608 can execute instructions across a plurality ofexecution channels. In a further embodiment, each thread executed on thegraphics execution unit 608 is executed on a different channel.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710. Other sizes and formats of instruction can be used.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a geometry pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general-purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of the geometry pipeline 820 or the media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, geometry pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to geometry pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled, the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into perpixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated logic units (e.g.,L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via adata port 856 to perform memory access and communicate with renderoutput pipeline components of the processor. In some embodiments,sampler 854, caches 851, 858 and execution units 852A-852B each haveseparate memory access paths. In one embodiment the texture cache 858can also be configured as a sampler cache.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front-end 834. In some embodiments, videofront-end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, the geometry pipeline 820 and media pipeline 830are configurable to perform operations based on multiple graphics andmedia programming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a client902, a command operation code (opcode) 904, and data 906 for the commandA sub-opcode 905 and a command size 908 are also included in somecommands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands Oncethe command is received by the client unit, the client unit reads theopcode 904 and, if present, sub-opcode 905 to determine the operation toperform. The client unit performs the command using information in datafield 906. For some commands an explicit command size 908 is expected tospecify the size of the command In some embodiments, the command parserautomatically determines the size of at least some of the commands basedon the command opcode. In some embodiments commands are aligned viamultiples of a double word. Other command formats can be used.

The flow diagram in FIG. 9B illustrates an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands In response toa pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments, execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general-purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates an exemplary graphics software architecture for adata processing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL), Direct3D, the OpenGL Shader Language(GLSL), and so forth. The application also includes executableinstructions 1014 in a machine language suitable for execution by thegeneral-purpose processor core 1034. The application also includesgraphics objects 1016 defined by vertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11A is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, reusable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh-level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 11B illustrates a cross-section side view of an integrated circuitpackage assembly 1170, according to some embodiments described herein.The integrated circuit package assembly 1170 illustrates animplementation of one or more processor or accelerator devices asdescribed herein. The package assembly 1170 includes multiple units ofhardware logic 1172, 1174 connected to a substrate 1180. The logic 1172,1174 may be implemented at least partly in configurable logic orfixed-functionality logic hardware, and can include one or more portionsof any of the processor core(s), graphics processor(s), or otheraccelerator devices described herein. Each unit of logic 1172, 1174 canbe implemented within a semiconductor die and coupled with the substrate1180 via an interconnect structure 1173. The interconnect structure 1173may be configured to route electrical signals between the logic 1172,1174 and the substrate 1180, and can include interconnects such as, butnot limited to bumps or pillars. In some embodiments, the interconnectstructure 1173 may be configured to route electrical signals such as,for example, input/output (I/O) signals and/or power or ground signalsassociated with the operation of the logic 1172, 1174. In someembodiments, the substrate 1180 is an epoxy-based laminate substrate.The package substrate 1180 may include other suitable types ofsubstrates in other embodiments. The package assembly 1170 can beconnected to other electrical devices via a package interconnect 1183.The package interconnect 1183 may be coupled to a surface of thesubstrate 1180 to route electrical signals to other electrical devices,such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic 1172, 1174 are electricallycoupled with a bridge 1182 that is configured to route electricalsignals between the logic 1172, 1174. The bridge 1182 may be a denseinterconnect structure that provides a route for electrical signals. Thebridge 1182 may include a bridge substrate composed of glass or asuitable semiconductor material. Electrical routing features can beformed on the bridge substrate to provide a chip-to-chip connectionbetween the logic 1172, 1174.

Although two units of logic 1172, 1174 and a bridge 1182 areillustrated, embodiments described herein may include more or fewerlogic units on one or more dies. The one or more dies may be connectedby zero or more bridges, as the bridge 1182 may be excluded when thelogic is included on a single die. Alternatively, multiple dies or unitsof logic can be connected by one or more bridges. Additionally, multiplelogic units, dies, and bridges can be connected together in otherpossible configurations, including three-dimensional configurations.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general-purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIGS. 13A-13B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 13A illustrates an exemplary graphics processor 1310 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to an embodiment. FIG. 13B illustrates anadditional exemplary graphics processor 1340 of a system on a chipintegrated circuit that may be fabricated using one or more IP cores,according to an embodiment. Graphics processor 1310 of FIG. 13A is anexample of a low power graphics processor core. Graphics processor 1340of FIG. 13B is an example of a higher performance graphics processorcore. Each of the graphics processors 1310, 1340 can be variants of thegraphics processor 1210 of FIG. 12 .

As shown in FIG. 13A, graphics processor 1310 includes a vertexprocessor 1305 and one or more fragment processor(s) 1315A-1315N (e.g.,1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). Graphicsprocessor 1310 can execute different shader programs via separate logic,such that the vertex processor 1305 is optimized to execute operationsfor vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations forfragment or pixel shader programs. The vertex processor 1305 performsthe vertex processing stage of the 3D graphics pipeline and generatesprimitives and vertex data. The fragment processor(s) 1315A-1315N usethe primitive and vertex data generated by the vertex processor 1305 toproduce a framebuffer that is displayed on a display device. In oneembodiment, the fragment processor(s) 1315A-1315N are optimized toexecute fragment shader programs as provided for in the OpenGL API,which may be used to perform similar operations as a pixel shaderprogram as provided for in the Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for the graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12 , such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

As shown FIG. 13B, graphics processor 1340 includes the one or moreMMU(s) 1320A-1320B, caches 1325A-1325B, and circuit interconnects1330A-1330B of the graphics processor 1310 of FIG. 13A. Graphicsprocessor 1340 includes one or more shader core(s) 1355A-1355N (e.g.,1455A, 1355B, 1355C, 1355D, 1355E, 1355F, through 1355N-1, and 1355N),which provides for a unified shader core architecture in which a singlecore or type or core can execute all types of programmable shader code,including shader program code to implement vertex shaders, fragmentshaders, and/or compute shaders. The exact number of shader corespresent can vary among embodiments and implementations. Additionally,graphics processor 1340 includes an inter-core task manager 1345, whichacts as a thread dispatcher to dispatch execution threads to one or moreshader cores 1355A-1355N and a tiling unit 1358 to accelerate tilingoperations for tile-based rendering, in which rendering operations for ascene are subdivided in image space, for example to exploit localspatial coherence within a scene or to optimize use of internal caches.

FIGS. 14A-14B illustrate additional exemplary graphics processor logicaccording to embodiments described herein. FIG. 14A illustrates agraphics core 1400 that may be included within the graphics processor1210 of FIG. 12 , and may be a unified shader core 1355A-1355N as inFIG. 13B. FIG. 14B illustrates an additional general-purpose graphicsprocessing unit 1430, which is a highly-parallel general-purposegraphics processing unit suitable for deployment on a multi-chip module.

As shown in FIG. 14A, the graphics core 1400 includes a sharedinstruction cache 1402, a texture unit 1418, and a cache/shared memory1420 that are common to the execution resources within the graphics core1400. The graphics core 1400 can include multiple slices 1401A-1401N orpartition for each core, and a graphics processor can include multipleinstances of the graphics core 1400. The slices 1401A-1401N can includesupport logic including a local instruction cache 1404A-1404N, a threadscheduler 1406A-1406N, a thread dispatcher 1408A-1408N, and a set ofregisters 1410A-1440N. To perform logic operations, the slices1401A-1401N can include a set of additional function units (AFUs1412A-1412N), floating-point units (FPU 1414A-1414N), integer arithmeticlogic units (ALUs 1416-1416N), address computational units (ACU1413A-1413N), double-precision floating-point units (DPFPU 1415A-1415N),and matrix processing units (MPU 1417A-1417N).

Some of the computational units operate at a specific precision. Forexample, the FPUs 1414A-1414N can perform single-precision (32-bit) andhalf-precision (16-bit) floating point operations, while the DPFPUs1415A-1415N perform double precision (64-bit) floating point operations.The ALUs 1416A-1416N can perform variable precision integer operationsat 8-bit, 16-bit, and 32-bit precision, and can be configured for mixedprecision operations. The MPUs 1417A-1417N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. The MPUs 1417-1417N can perform avariety of matrix operations to accelerate machine learning applicationframeworks, including enabling support for accelerated general matrix tomatrix multiplication (GEMM). The AFUs 1412A-1412N can performadditional logic operations not supported by the floating-point orinteger units, including trigonometric operations (e.g., Sine, Cosine,etc.).

As shown in FIG. 14B, a general-purpose processing unit (GPGPU) 1430 canbe configured to enable highly-parallel compute operations to beperformed by an array of graphics processing units. Additionally, theGPGPU 1430 can be linked directly to other instances of the GPGPU tocreate a multi-GPU cluster to improve training speed for particularlydeep neural networks. The GPGPU 1430 includes a host interface 1432 toenable a connection with a host processor. In one embodiment the hostinterface 1432 is a PCI Express interface. However, the host interfacecan also be a vendor specific communications interface or communicationsfabric. The GPGPU 1430 receives commands from the host processor anduses a global scheduler 1434 to distribute execution threads associatedwith those commands to a set of compute clusters 1436A-1436H. Thecompute clusters 1436A-1436H share a cache memory 1438. The cache memory1438 can serve as a higher-level cache for cache memories within thecompute clusters 1436A-1436H.

The GPGPU 1430 includes memory 1444A-1444B coupled with the computeclusters 1436A-1436H via a set of memory controllers 1442A-1442B. Invarious embodiments, the memory 1434A-1434B can include various types ofmemory devices including dynamic random access memory (DRAM) or graphicsrandom access memory, such as synchronous graphics random access memory(SGRAM), including graphics double data rate (GDDR) memory.

In one embodiment the compute clusters 1436A-1436H each include a set ofgraphics cores, such as the graphics core 1400 of FIG. 14A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for machine learning computations. For example and in oneembodiment at least a subset of the floating point units in each of thecompute clusters 1436A-1436H can be configured to perform 16-bit or32-bit floating point operations, while a different subset of thefloating point units can be configured to perform 64-bit floating pointoperations.

Multiple instances of the GPGPU 1430 can be configured to operate as acompute cluster. The communication mechanism used by the compute clusterfor synchronization and data exchange varies across embodiments. In oneembodiment the multiple instances of the GPGPU 1430 communicate over thehost interface 1432. In one embodiment the GPGPU 1430 includes an I/Ohub 1439 that couples the GPGPU 1430 with a GPU link 1440 that enables adirect connection to other instances of the GPGPU. In one embodiment theGPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of theGPGPU 1430. In one embodiment the GPU link 1440 couples with a highspeed interconnect to transmit and receive data to other GPGPUs orparallel processors. In one embodiment the multiple instances of theGPGPU 1430 are located in separate data processing systems andcommunicate via a network device that is accessible via the hostinterface 1432. In one embodiment the GPU link 1440 can be configured toenable a connection to a host processor in addition to or as analternative to the host interface 1432.

While the illustrated configuration of the GPGPU 1430 can be configuredto train neural networks, one embodiment provides alternateconfiguration of the GPGPU 1430 that can be configured for deploymentwithin a high performance or low power inferencing platform. In aninferencing configuration the GPGPU 1430 includes fewer of the computeclusters 1436A-1436H relative to the training configuration.Additionally, the memory technology associated with the memory1434A-1434B may differ between inferencing and training configurations,with higher bandwidth memory technologies devoted to trainingconfigurations. In one embodiment the inferencing configuration of theGPGPU 1430 can support inferencing specific instructions. For example,an inferencing configuration can provide support for one or more 8-bit(or other sized) integer dot product instructions, which are commonlyused during inferencing operations for deployed neural networks.

Examples of Executions of Multiple Commands

A traditional way of mapping compute contexts to compute resources(e.g., execute units (EUs)) involves static allocation using software.But to scale up mapping of compute contexts to compute resources onlarger graphics processing units (GPUs), static allocation or involvingsoftware to intervene for scaling up may not be feasible for machineutilization or performance. In addition, historically, an entire GPU hasbeen provisioned to process either 3D contexts or compute contexts butnot both and so a GPU may not be able to scale to process differenttypes and numbers of contexts.

A GPU performs work based on submitted contexts. In some GPU systems,submitted contexts are executed serially. For example, a GPU reads dataassociated with contexts from memory, performs work on the data usingassociated kernels or processes, and writes results to memory. Forserial execution of contexts, data isolation concerns can arise betweensteps of memory read and write. According to some embodiments, to assistwith data isolation, the GPU state can be cleared between contextsubmissions.

Various embodiments allow for independent applications to executeworkloads at the same time using a shared computing resource such as agraphics processing unit (GPU). Various embodiments can supportasynchronous concurrent execution of two or more contexts of the same ordifferent type from different applications using a shared computingresource. A computing resource can automatically manage the computeassets dynamically based on the number of active running computecontexts from one or more compute context streamers. For example, acompute resource can use a workload mapping table to map a context toone or more segments of the compute resource for execution. Anapplication or driver may not be used to intervene to manage the computeresource activity every time a context terminates or becomes active. Insome embodiments, execution of active contexts can continue while newcontexts are received.

For example, in a situation where a first (single) compute contextstreamer provides contexts for execution and a compute resource providesfour quadrants of execution units, then all four quadrants can beallocated to execution of the compute contexts from the first computecontext streamer. After completion of execution of compute contexts fromthe first compute context streamer in a quadrant, the quadrant canreturn to a state of inactivity and be available for execution of aworkload associated with the first compute context streamer.

In the event a compute context from a second compute context streamer isreceived while any context associated with the first compute contextstreamer is executed on a quadrant, the context associated with thesecond compute context streamer is assigned to a particular quadrant forexecution according to a workload distribution scheme. If the assignedquadrant is executing a workload associated with a context from thefirst compute context streamer, then the workload associated with thesecond compute context streamer is provided for execution by theassigned quadrant after the assigned quadrant has completed executingthe workload associated with the first compute context streamer. If theassigned quadrant is inactive or idle, then the workload (e.g., threads,commands, or contexts) associated with the second compute contextstreamer is provided for execution by the assigned quadrant. Accordingto the workload distribution scheme for two active compute contextstreamers, workloads associated with the first compute context streamercan be provided to the quadrants assigned by the workload distributionscheme but not to quadrants assigned for execution of workloads from thesecond compute context streamer.

Receipt of a third compute context while workloads from first and secondcompute context streamers are actively executed can cause allocation ofcompute contexts according to a workload distribution scheme amongquadrants for three compute context streamers. Likewise, receipt of afourth compute context while workloads from first, second, and thirdcompute context streamers are actively executed can cause allocation ofcompute contexts according to a workload distribution scheme amongquadrants for four compute context streamers.

In the event a quadrant has completed execution of a workload and acompute context streamer assigned to the quadrant provides no additionalworkloads, the quadrant can be available for allocation according to theworkload distribution scheme based on the number of active contexts fromcompute context streamer(s). For example, two context streamers haveactive workloads and a first compute context streamer is assigned tofirst and second quadrants and a second compute context streamer isassigned to third and fourth quadrants. In the event the first computecontext streamer has no additional workloads (e.g., threads, commands,or contexts), the workload distribution scheme can cause workloadsassociated with the second compute context streamer to be executed onfirst, second, third and fourth quadrants after workloads associatedwith the first compute context streamer have completed execution on thefirst and second quadrants.

FIG. 15 depicts an example environment. Application 1502 can generatecommands for processing associated data for storage in Command (Cmd)Buffer 1504 and data buffer 1506. The commands can also includereferences to data stored in memory, such as but not limited to vertexand geometry data and/or image data and memory objects. Processingelement 1520 can be one or more of: a rendering engine, execution unit,graphics processing unit, central processing unit, accelerator, fieldprogrammable gate array, and so forth. Command streamer 1522 can providea stream of commands for example from an application. Thread dispatcher1524 can dispatch threads on execution units (EUs) 1532 for execution.In this example, processing element 1520 can include one or more dualsubslice (DSS) 1530 with one or more execution units (EUs) 1532. An EU1532 can execute a portion of a command via execution of a thread andits associated kernel. Processing element can use a memory 1536 andcache 1538 for execution of threads and storing results. Data andresults can be copied to system memory 1540 or last level cache 1542associated with one or more cores or CPUs.

FIG. 16 depicts an example process. The process can be performed usingan environment described with respect to FIG. 15 , although otherenvironments can be used such as that described with respect to FIG. 17Aor another similar or different computing environment. At 1602, anapplication prepares data and enqueues work (e.g., command, kernel, andcontext) for execution by a processing element. At 1604, a driver for aprocessing element can submit the work to the processing element. At1606, the processing element executes a next command. At 1608, a threadand associated kernel are dispatched. For example, a hardware dispatchengine (e.g., thread dispatch engine) can dispatch threads. At 1610, oneor more execution units run any ready-to-run thread. For example, aready-to-run thread can have an associated kernel for computes andloads/stores. An EU switches to a next thread on a memory fetch orregister stalls, among others. When a thread terminates, the EU storesresults and states to memory and accepts another thread for execution.At 1612, a determination is made as to whether a last command is reachedfor submitted work. If a last command is not reached for submitted work,then 1608 follows. If a last command is reached for submitted work, then1614 follows. At 1614, the application is notified that queued work iscompleted.

FIG. 17A depicts an example graphics processing unit system. In someexamples, a global compute front end (CFEG) 1704 can receive commandsfrom render command streamer (RCS) 1706 and asynchronous compute contextstreamers (CCS) 1702-0 to 1702-3, although different numbers of RCS andCCS can be supported. CFEG 1704 can use, provide or act as a command orthread dispatch engine. A compute command streamer (e.g., CCS0 1702-0 toCCS3 1702-3) can receive and interpret an asynchronous compute context.Incidentally, compute contexts can be provided through a dispatchportion using an MMIO address by an application for example. A MMIOaddress can be associated with a CCS and a software driver andmicrocontroller can route requests to a specific CCS or any CCS. CCS1702-0 to 1702-3 can provide compute contexts to CFEG 1704 fordistribution to one or more CFE 1706-0 to 1706-3. For example, a computecontext can define data, variables, conditions, kernels, commands,source and destination memory locations, and other information orcommands used to perform operations on data. A CCS allows a programmeror application to select the type of computation to perform as opposedto invoking multiple stage processing. Examples of applications usingcompute command streamers include matrix applications (e.g., machinelearning), physical modelling in games, high performance compute engines(e.g., chemical reactions). CFE 1706-0 to 1706-3 can generate thread(s)from compute contexts using a single compute stage.

CFEG 1704 can use a mapping table to select which of CFE 1706-0 to1706-3 to receive contexts, workloads, threads, or commands from one ormore CCS0-CCS3 or RCS 1700. A command, workload, or thread can includeor generate multiple commands, workloads, or threads. For example, themapping table can be implemented as a state machine or programmabletable that specifies work allocation from one or more of CCS0-CCS3 to acompute front end (CFE) 1706-0 to 1706-3. An example mapping table isdescribed with respect to FIG. 20 , although other schemes can be used.Based on whether a CFE 1706-0 to 1706-3 is processing a workloadassociated with a context and a source of a workload, CFEG 1704 canallocate the workload or thread to a specific CFE according to themapping table. CFEG 1704 can provide, use or act as a thread schedulerto allocate threads for execution. If the CFE specified by the mappingtable to handle a workload from CCS is available or inactive, CFEG 1704can send work to the specified CFE. If the CFE specified by the mappingtable to handle a workload from a CCS is active handling work for thesame CFE, CFEG 1704 can wait for the CFE to complete work or wait foranother CFE, (mapped to receive commands from the CCS) that is free andsend the work to that CFE. CFEG 1704 can send work to a CFE that isavailable for processing and does not need to stop active workloads on aparticular CFE. After state and data are available from EUs associatedwith a CFE, that information can be copied and the EUs associated with aCFE can be available to perform work. Accordingly, CFEG 1704 candynamically allocate one or more DSSs to execute a workload from a CCSor RCS and manage transition from inactive state to performance of aworkload allocated by the mapping table, completion of the workload, tocommencement of a workload from the same or different CCS according tothe mapping table.

CFEG 1704 can dispatch workloads from RCS 1700 to a least loaded DSS butCCS workloads can be allocated using a mapping table and can only besent to a permitted DSS (according to the mapping table). For example,CFEG 1704 can receive inputs from CCS0 1702-0 to CCS3 1702-3 and inputsfrom RCS 1700 and distribute work from CCS0 1702-0 to CCS3 1702-3 to CFE1706-0 to 1706-3 based on a workload mapping table. CFEG 1704 canperform dynamic load balance of workloads sent to a CFE from a CCS. Insome embodiments, CFEG 1704 can break work into smaller pieces. Forexample, for a 1000 threads workload, 10 threads can be allocated to aCFE in a batch until all threads are completed.

CFE 1706-0 to 1706-3 can allocate (e.g., dispatch) workloads torespective quadrants 0 to 3 and each quadrant can be associated with oneor more dual subslices (DSSs) available for execution of threads. CFE1706-0 to 1706-3 can perform load balancing on DSSs. A DSS can runworkloads or threads (e.g., kernels and/or code) provided from a CCS01702-0 to CCS3 1702-3 or RCS 1700. A DSS can be implemented as anexecution unit, processor, core, fixed function device, fieldprogrammable gate array (FPGA), programmable logic control (PLC),application specific integrated circuit (ASIC), and so forth. In someembodiments, DSSs can provide homogenous compute capabilities. In someexamples, workloads from RCS 1700 can run on any compute assets (e.g.,DSS) in the system, but workloads from a CCS on the other hand can beallocated to run on specific quadrants based on the activity of theother CCS contexts and the mapping table. In some examples, a DSS canonly accept workloads from 1 of 4 CCS at a time but any DSS can receiveworkloads from RCS 1700. In some examples, every thread executed by aDSS has an associated identifier to a context so a DSS thread can trackan associated context for a thread.

Restricting CCS to allocating workloads to specific quadrants can limitan amount of state stored for use by a quadrant of DSS and limit theamount of memory used to store context so that workloads allocated bythe CCS can share state or context. State for workloads from an RCS canbe shared among multiple quadrants.

RCS 1700 can run 3D graphics processing commands or compute commands anddispatch 3D render compute contexts for execution by one or more dualsubslices (DSS) via CFEG 1704 or vertex fetch global unit (VFG) 1720.VFG 1720 can perform load balancing of vertex processing. RCS 1700 cangenerate and dispatch threads to a multi-stage fixed 3D graphicspipeline to move computation through the 3D pipeline, in sequence. RCS1700 can setup states of pipeline (e.g., 3D render context) based on adraw command where a pipeline can include one or more of: a vertexshader, hull shader, geometry shader, pixel shader, hashing pixelshaders, tessellation, and so forth. In some examples, DSS can acceptworkloads for use in OpenGL or DirectX compliant graphics pipelines,among others.

Various embodiments can use CFEG 1704 to manage workload distributionsto DSSs without software synchronization such as pipe control andflushes that could limit performance.

FIG. 17B depicts an example global compute front end. In this example,RCS queue 1752 can receive and enqueue commands from an RCS, althoughother numbers of queues can be used. CCS0 queue 1754-0 to CCS3 queue1754-3 can receive and enqueue commands from respective CCS0 to CCS3,although other numbers of queues can be used. Allocator 1758 candetermine which quadrant or computing resource to allocate to perform acommand based on the compute context streamer(s) that have activecommands for performance. Mapping table 1756 can indicate which quadrantor computing resource to allocate to perform a command from a computecontext streamer. An example mapping table is described for example withrespect to FIG. 20 . Quadrant ownership transfer device 1760 can manageownership change of a quadrant or computing resource when a computecontext streamer is to use a quadrant or computing resource after adifferent compute context streamer uses the same quadrant or computingresource. For example, quadrant ownership transfer device 1760 can flushthe write data buffer of the quadrant(s) to cache (e.g., level 3 cache),invalidate the state and constant caches, and/or propagate the statevalues to the shared function units (e.g., DSS units). The state valuescan be pointers to the location of the surface_state, binding table, andso forth.

FIG. 18 depicts an example of distribution of work. In this example,CFEG 1802 distributes compute work from CCS0 to CCS3 and RCS 1804 to oneor more of CFE 1806-0 to 1806-3. For a CCS (CCS0 to CCS3), a generalpurpose command streamer (GPCMD) tracks commands requested forexecution. GPCMD executes a COMPUTE_WALKER command to cause execution ofa kernel over one or more thread group dispatches. For example, based ona mapping table of CCS to CFE (and associated quadrant), a GPCMD candispatch batches of 1 to 16 thread groups to a CFE every cycle. CFEG1802 can provide prioritization of context forwarding among contextsfrom CCSs and RCS. A CFE can support active contexts from an RCS and oneCCS. In some examples, a higher priority context from an RCS or CCS canbe provided for dispatch to a CFE and its associated quadrant.

Load balancing unit 1808 manages the transition of CFE ownership fromone context to another. Load balancing unit 1808 can wait for acontext's thread dispatches to finish and then set up the state for thenew owning context.

In some embodiments, a state from any preempted GPCMD is saved incontext image in a common interface to a memory unit, e.g., globaladdressing unit for command streamers (GACS).

FIG. 19 depicts an example of context executions. Threads associatedwith RCS and CCS context dispatches can be provided to a DSS using alimited bus resource. RCS and CCS thread dispatches can arrive at a DSSin parallel. Virtual channels can be provided to every DSS whereby QID0is used to identify threads from RCS and QID1 is used to identifythreads from a CCS. For a DSS, a single CCS can dispatch a thread at atime. Running contexts can be submitted to a command streamer, where acommand streamer is assigned a QID. The 3D command stream is assigned aQID of QID0 whereas compute command streamers are assigned a QID ofQID1. Thread dispatch 1902 can dispatch a thread with an associated QID(e.g., QID0 or QID1). A command streamer's active page table is assigneda unique EXID and the EXID tag is used with every memory address formemory caches and page table translations. In some embodiments, a GPUsupports one 3D command streamer simultaneous with zero to four activecompute command streamers. The dispatched thread can be a request toperform a workload, thread execution, or graphics processing operation.

Thread dispatch 1902 allocates a free thread, its barrier, and sharedlocal memory (SLM). On thread allocation, thread dispatch 1902 clearsgeneral purpose register file (GRF), the thread's barrier, and SLM. Inthis example, caches associated with threads having QID0 and QID1 areflushed when a QID context changes. A dispatched thread can execute onan execution unit (EU).

A DSS partition of a GPU that includes one or more execution units (EUs)can simultaneously run two contexts: one QID0 and one QID1. Eachexecuted thread has its own QID, registers (e.g., GRF), shared localmemory (SLM) base/limit (e.g., memory resource used by DSS to read/writememory). Multiple EUs can execute different threads in parallel. Sharedfunction caches are tagged using a QID. Shared local memory accesses arebound-checked based on a per-thread limit.

In order to attempt to provide for data isolation among threads, a DSSshared resource can use the QID tag to isolate two different computecontexts, both QID1, running separately on the same DSS (or portionthereof) only after the previous QID1's old data has been cleared.Global addressing for DSS units (GADSS) provides for arbitration amongmemory requesters inside DSS to select memory request and issue memoryrequest and route content to a requester. EXID[QID] can indicate amemory address entry location for a context (e.g., inside level 3 cacheand page table translation).

FIG. 20 depicts an example resource allocation scheme. Variousembodiments can use a workload mapping table to map a current activestate tuple to a CFE cluster (e.g., C-Slice or CSlice) as allocated to aparticular compute context streamer (CCS). A CCS can be considered Idle(I) or Active (A). The “A” label means that a workload from a CCS isactively executing on a quadrant and the “I” label means that the CCS isIDLE (e.g., a quadrant is not executing a workload). A mapping tabledefines an “active state” tuple for CCS0, CCS1, CCS2, and CCS3 (shown asrespective C0, C1, C2, and C3) for 16 cases, although other numbers ofcases can be handled. When the active state tuple changes, a globalcompute front end (CFEG) slice allocator shifts C-slice (e.g., quadrant)ownership. The priority of a CCS context can be ignored whenre-balancing slice ownership.

Based on the mapping table system with 4 C-slices, each C-slice ismapped to perform threads from a particular CCS. Before any context issubmitted for execution, all C-slice quadrants are in an inactive state.For a single CCS providing contexts for work, all C-slices are allocatedfor processing contexts from the single CCS. The row entitled “0 or 1Active CCS” provides an example of allocation of a C-Slice forprocessing a context from a single CCS. A C-Slice can include one ormore DSS. For example, contexts from CCS0 can be allocated to allC-Slices (shown as C0), contexts from CCS1 can be allocated to allC-Slices (shown as C1), and so forth.

The row entitled “2 Active CCS” provides an example of allocation ofC-Slices for processing contexts from a two CCSs. For example, contextsfrom CCS0 and CCS1 are allocated for processing by C-Slices whereby halfof a CFE, cluster executes contexts from CCS0 (e.g., Cslice-0 andCslice-2) and another, different, half executes contexts from CCS1(e.g., Cslice-1 and Cslice-3). A more specific example is 8 DSSs areallocated to a CFE cluster and 4 DSSs are allocated for processingcontexts from CCS0 and 4 DSSs are allocated for processing contexts fromCCS1.

The row entitled “3 or 4 Active CCS” provides an example of allocationof C-Slices for processing a context from three or four CCSs. Forexample, contexts from CCS0, CCS1, and CCS2 are allocated for processingby C-Slices whereby a quarter of a CFE cluster executes contexts fromCCS0 (e.g., Cslice-0), a quarter of a CFE cluster executes contexts fromCCS1 (e.g., Cslice-1), and a half of a CFE cluster executes contextsfrom CCS2 (e.g., Cslice-2 and Cslice-3). A more specific example is 8DSSs are allocated to a CFE cluster and 2 DSSs are allocated forprocessing contexts from CCS0, 2 DSSs are allocated for processingcontexts from CCS1, and 4 DSSs are allocated for processing contextsfrom CCS2.

Note that the ownership mapping tables can be adjusted so that any DSSscan be selected for processing a context from a CCS. Note also that forallocations of 3 Active CCSs, any CCS can be chosen for allocation of50% of CFE cluster processing resources. In some cases, if a highernumber of workloads arrives from a CCS, then the CCS can be allocated50% of processing resources and the other two CCSs are allocated 25% ofprocessing resources each.

For example, contexts from CCS0, CCS1, CCS2, and CCS3 are allocated forprocessing by C-Slices whereby a quarter of a CFE cluster executescontexts from CCS0 (e.g., Cslice-0), a quarter of a CFE cluster executescontexts from CCS1 (e.g., Cslice-1), a quarter of a CFE cluster executescontexts from CCS2 (e.g., Cslice-2), and a quarter of a CFE clusterexecutes contexts from CCS3 (e.g., Cslice-3). A more specific example is8 DSSs are allocated to a CFE cluster and 2 DSSs are allocated forprocessing contexts from CCS0, 2 DSSs are allocated for processingcontexts from CCS1, 2 DSSs are allocated for processing contexts fromCCS2, and 2 DSSs are allocated for processing contexts from CCS3. Notethat the ownership mapping tables can be adjusted so that any DSSs canbe selected for processing a context from a CCS.

Next, an example description is provided of a manner transferringbetween an active CCS state or to a non-active CCS state whereby nocontext or workload from a CCS is executing using a CFE cluster (e.g.,quadrant). When a graphics processing engine changes from one active CCS(e.g., CCS0 active) to two active CCSs (e.g., CCS0 and CCS1), some ofthe CSlices that were running threads from CCS0 are allocated to runthreads from CCS1. For example, when CCS0 is the only active CCS,C-Slice0 to C-Slice3 are allocated for running threads from CCS0.Transition to running workloads from CCS0 could involve swapping ofCSlice-1 and CSlice-3 from use by CCS0 to use by CCS1 after workexecuted by CSlice-1 and CSlice-3 completes. Similarly, when going fromtwo active CCS (CCS0 and CCS1) to one active (CCS0), workloads aredistributed from the CCS0 to all C-slices.

CCS0 to CCS3 (represented by C0-C3) can use different MMIO ports forcontext submission (e.g., work submissions). In the example, where C0 isrunning contexts from CCS0 and a context from CCS1 is submitted througha MMIO port, the system can wait for CSlices-1 and 3 to finish, thenallow dispatch of a context from CCS1 to bottom quadrants (CSlices-1 and3). In addition, work dispatched from CCS0 can be provided to CSlice-0or CSlice-2. After CSlice-1 and 3 finish their workload and no morecontexts are available from CCS1, then the four quadrants (e.g.,CSlices-0 to 3) can be allocated to handle work from CCS0. Afterfinishing work from CCS0, then all quadrants can become inactive.

FIG. 21 depicts an example of movement between states. For example, ininactive state 2102, all CSlices are idle. After a CCS0 dispatches oneor more threads that are mapped to run on all 4 Cslices(Cslice1-Cslice3), the state changes to state 2104. A softwareapplication submits a compute walker command using CCS1. Based on oneexample mapping table, the command from CCS1 can be run on Cslice1 andCslice3. CFEG stops from dispatching threads from CCS0 to Cslice1 andCslice3. CFEG waits for all running threads from CCS0 to complete onCslice1 and Cslice3 but allows CCS0 to continues to dispatch threads onCslice0 and Cslice2. CFEG flushes the write data buffer of the Cslice1and Cslice 3 to cache (e.g., level 3 cache) to ensure that the writedata is globally observable and accessible. CFEG invalidates the stateand constant caches of CCS0. Before running threads of CCS1 on Cslice1and Cslice3, the state values are propagated to the shared functionunits in Cslice1 and Cslice3 (e.g., DSS units). The state values can bepointers to the location of the surface_state, binding table, and soforth. After propagating the state values, CFEG starts dispatching CCS1threads to Cslice1 and Cslice3 and the state changes to state 2106.

The following example describes a case of state 2110 where commands fromCCS0 are running on Cslice0 and Cslice2 whereas commands from CCS1 arerunning on Cslice1 and Cslice3. Commands from CCS1 have completed or arepreempted and Cslice1 and Cslice3 are free. CFEG prepares the Cslice1and Cslice3 to start running threads for CCS0 so that Cslice0-Cslice3run threads for CCS0 at state 2112.

Note that a slice can be preempted by another CCS if an applicationindicates preemption is to be applied. For example, preemption caninclude allowing threads on a slice to complete, saving state and data,and running threads associated with the command that invokes preemption.A CFEG can stop dispatches to the preempted slice and wait fordispatched threads to complete. Threads that have not been dispatchedcan be resumed on the same slice (after preemptive threads complete) orusing another slice.

FIG. 22 depicts an example of time taken for processing contexts. Thevertical axis represents EU utilization and the horizontal accessrepresents time. The examples show time taken to complete processing asubmitted context for three scenarios: context preemption, dual-contextsubmission, and multi-context submission. In the example of contextpreemption, an actively processed context is replaced. Dual-contextsubmission allows for contexts to be submitted to execution unitswithout replacing an active context. Multi-context submission allows foran active context to complete and the EU that processed the activecontext to process another context. As is shown, dual-context submissionand multi-context submission can allow for submitted contexts tocommence execution sooner than a case of context preemption.

FIG. 23 depicts an example process. At 2302, a command from a streameris received. The command can be received from one of multiple computecontext streamers. Compute context streamers can receive contexts fromone or more applications. The command can be based on a compute contextor a render context. For example, a compute context can define data,variables, conditions, kernels, commands, source and destination memorylocations, and other information or commands used to perform operationson data. At 2304, a determination can be made as to which processingresource to use to perform the command. For example, a mapping table canbe used to allocate a command to a processing resource based on a sourcecompute context streamer and which compute context streamer has anactively executed command. For example, a computing resource can includemultiple processing resources and commands from a particular computecontext streamer can be allocated for execution by a particularprocessing resource. A computing resource can be a GPU, CPU, GPGPU. Aprocessing resource can include one or more of: a DSS, execution unit,processor, core, fixed function device, field programmable gate array(FPGA), programmable logic control (PLC), application specificintegrated circuit (ASIC), and so forth. At 2306, the command isallocated to a determined processing resource for execution.

At 2308, a determination can be made as to whether the determinedprocessing resource to perform the command is available to perform thecommand. For example, the determined processing resource is available toperform the command if the processing resource is allocated to performcommands from the same compute context streamer and 2310 follows. Forexample, the determined processing resource is not available to performthe command if the determined processing resource is performing anothercommand from a different compute context streamer than that whichprovided the command and 2320 follows.

At 2310, the command is allocated to use the determined processingresource. A command can be represented using one or more threads. Forexample, if there is a queue for one or more threads associated with acommand, then the one or more threads are added to the queue and can beperformed in turn.

At 2320, the determined processing resource is allocated as permitted toperform commands from a second compute context streamer. The secondcompute context streamer can be a compute context streamer that providedthe command at 2302. One or more threads can represent a command and beprovided for execution. At 2322, the write data buffer of the processingresource are flushed to cache (e.g., level 3 cache) to provide for thewrite data as observable and accessible and the state and constantcaches of the former compute context streamer are invalidated. Inaddition, at 2324, state values of the second compute context streamerare propagated to shared function units of the determined processingresource. Enqueued commands can be moved and allocated to be performedby another processing resource.

Various examples may be implemented using hardware elements, softwareelements, or a combination of both. In some examples, hardware elementsmay include devices, components, processors, microprocessors, circuits,circuit elements (e.g., transistors, resistors, capacitors, inductors,and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memoryunits, logic gates, registers, semiconductor device, chips, microchips,chip sets, and so forth. In some examples, software elements may includesoftware components, programs, applications, computer programs,application programs, system programs, machine programs, operatingsystem software, middleware, firmware, software modules, routines,subroutines, functions, methods, procedures, software interfaces, APIs,instruction sets, computing code, computer code, code segments, computercode segments, words, values, symbols, or any combination thereof.Determining whether an example is implemented using hardware elementsand/or software elements may vary in accordance with any number offactors, such as desired computational rate, power levels, heattolerances, processing cycle budget, input data rates, output datarates, memory resources, data bus speeds and other design or performanceconstraints, as desired for a given implementation. It is noted thathardware, firmware and/or software elements may be collectively orindividually referred to herein as “module,” “logic,” “circuit,” or“circuitry.”

Some examples may be implemented using or as an article of manufactureor at least one computer-readable medium. A computer-readable medium mayinclude a non-transitory storage medium to store logic. In someexamples, the non-transitory storage medium may include one or moretypes of computer-readable storage media capable of storing electronicdata, including volatile memory or non-volatile memory, removable ornon-removable memory, erasable or non-erasable memory, writeable orre-writeable memory, and so forth. In some examples, the logic mayinclude various software elements, such as software components,programs, applications, computer programs, application programs, systemprograms, machine programs, operating system software, middleware,firmware, software modules, routines, subroutines, functions, methods,procedures, software interfaces, API, instruction sets, computing code,computer code, code segments, computer code segments, words, values,symbols, or any combination thereof.

According to some examples, a computer-readable medium may include anon-transitory storage medium to store or maintain instructions thatwhen executed by a machine, computing device or system, cause themachine, computing device or system to perform methods and/or operationsin accordance with the described examples. The instructions may includeany suitable type of code, such as source code, compiled code,interpreted code, executable code, static code, dynamic code, and thelike. The instructions may be implemented according to a predefinedcomputer language, manner or syntax, for instructing a machine,computing device or system to perform a certain function. Theinstructions may be implemented using any suitable high-level,low-level, object-oriented, visual, compiled and/or interpretedprogramming language.

One or more aspects of at least one example may be implemented byrepresentative instructions stored on at least one machine-readablemedium which represents various logic within the processor, which whenread by a machine, computing device or system causes the machine,computing device or system to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

The appearances of the phrase “one example” or “an example” are notnecessarily all referring to the same example or embodiment. Any aspectdescribed herein can be combined with any other aspect or similar aspectdescribed herein, regardless of whether the aspects are described withrespect to the same figure or element. Division, omission or inclusionof block functions depicted in the accompanying figures does not inferthat the hardware components, circuits, software and/or elements forimplementing these functions would necessarily be divided, omitted, orincluded in embodiments.

Some examples may be described using the expression “coupled” and“connected” along with their derivatives. These terms are notnecessarily intended as synonyms for each other. For example,descriptions using the terms “connected” and/or “coupled” may indicatethat two or more elements are in direct physical or electrical contactwith each other. The term “coupled,” however, may also mean that two ormore elements are not in direct contact with each other, but yet stillco-operate or interact with each other.

The terms “first,” “second,” and the like, herein do not denote anyorder, quantity, or importance, but rather are used to distinguish oneelement from another. The terms “a” and “an” herein do not denote alimitation of quantity, but rather denote the presence of at least oneof the referenced items. The term “asserted” used herein with referenceto a signal denote a state of the signal, in which the signal is active,and which can be achieved by applying any logic level either logic 0 orlogic 1 to the signal. The terms “follow” or “after” can refer toimmediately following or following after some other event or events.Other sequences of steps may also be performed according to alternativeembodiments. Furthermore, additional steps may be added or removeddepending on the particular applications. Any combination of changes canbe used and one of ordinary skill in the art with the benefit of thisdisclosure would understand the many variations, modifications, andalternative embodiments thereof.

Disjunctive language such as the phrase “at least one of X, Y, or Z,”unless specifically stated otherwise, is otherwise understood within thecontext as used in general to present that an item, term, etc., may beeither X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z).Thus, such disjunctive language is not generally intended to, and shouldnot, imply that certain embodiments require at least one of X, at leastone of Y, or at least one of Z to each be present. Additionally,conjunctive language such as the phrase “at least one of X, Y, and Z,”unless specifically stated otherwise, should also be understood to meanX, Y, Z, or any combination thereof, including “X, Y, and/or Z.”′

1-20. (canceled)
 21. An apparatus comprising: a graphics processing unit(GPU) including a plurality of processing resources and circuitry todispatch at least one command for execution by the GPU, wherein thecircuitry is to: based on a configuration, permit execution of a firstcommand of the at least one command by one or more particular processingresources of the GPU based on a source of the first command, wherein theconfiguration is to indicate one or more particular processing resourcesof the GPU permitted to execute commands from one or more particularsources.
 22. The apparatus of claim 21, wherein in response to receiptof a second command from a second source while the first command isexecuting, the circuitry is to: based on the configuration indicatingthat the second source is permitted to execute a command on the one ormore particular processing resources that execute the first command:permit the first command to complete execution on the one or moreparticular processing resources and allocate the second command forexecution on one or more particular processing resources that previouslyexecuted the first command.
 23. The apparatus of claim 22, wherein thecircuitry is to: after completion of the first command, flush a writedata buffer to a cache and invalidate state and constant cachesassociated with the one or more particular processing resources thatexecuted the first command.
 24. The apparatus of claim 22, wherein thecircuitry is to: in response to detection of completion of the secondcommand and an unexecuted command from the source of the first command,allocate one or more of the processing resources formerly allocated toexecute the second command to perform the unexecuted command from thesecond source.
 25. The apparatus of claim 22, wherein the first commandis associated with a compute context or a render context and based oncompletion of execution of the first command, permit access to thecompute context or the render context for use by the second command. 26.The apparatus of claim 21, wherein the circuitry is to: in response toreceipt of a third command associated with a third source, allocate oneor more of the processing resources to perform the third command basedon the configuration.
 27. The apparatus of claim 21, comprising a memorydevice communicatively coupled to the circuitry to dispatch at least onecommand for execution by the GPU, wherein the memory device is to storethe configuration.
 28. The apparatus of claim 21, comprising one or moreof: a general purpose graphics processing unit or a central processingunit, wherein the general purpose graphics processing unit or thecentral processing unit is to execute a process that is a source of thefirst command.
 29. A method comprising: dispatching a first command forexecution by a first set of one or more processing resources of agraphics processing unit (GPU) based on a first configuration thatindicates the first set of one or more particular processing resourcesof the GPU that are permitted to execute commands from one or moreparticular sources.
 30. The method of claim 29, wherein the firstcommand is associated with a first source and comprising: based on asecond configuration that indicates a second set of one or moreparticular processing resources of the GPU permitted to performoperations for the one or more particular sources of the first command,dispatching a second command to the second set of one or more particularprocessing resources of the GPU, wherein the second set of one or moreparticular processing resources of the GPU is at least partiallydifferent than the first set of one or more particular processingresources of the GPU, and wherein the second command is provided by theone or more particular sources of the first command.
 31. The method ofclaim 29, comprising: after completion of the first command, flushing awrite data buffer to a cache and invalidating state and constant cachesassociated with the one or more particular processing resources thatexecuted the first command.
 32. The method of claim 29, comprising: inresponse to receipt of a third command from a second source while thefirst command is executing: based on the first configuration indicatingthat the second source is permitted to execute a command on the one ormore particular processing resources that execute the first command:permitting the first command to complete execution on the first set ofone or more particular processing resources, allocating the thirdcommand for execution on one or more particular processing resourcesthat previously executed the first command, and in response tocompletion of the third command and an unexecuted command from the oneor more particular sources of the first command, based on the firstconfiguration, allocating one or more of the particular processingresources formerly allocated to execute the third command to perform theunexecuted command from the second source.
 33. The method of claim 30,wherein the first command is associated with a compute context or arender context and based on completion of execution of the firstcommand, permitting access to the compute context or the render contextfor use by the second command.
 34. The method of claim 32, comprising:in response to receipt of a fourth command associated with a thirdsource, allocating one or more of the particular processing resources toperform the fourth command based on the first configuration.
 35. Atleast one non-transitory computer-readable medium comprisinginstructions stored thereon, that if executed by one or more processors,cause the one or more processors to: dispatch a first command forexecution by a first set of one or more processing resources of agraphics processing unit (GPU) based on a first configuration thatindicates the first set of one or more particular processing resourcesof the GPU are restricted to execute commands from one or moreparticular sources.
 36. The non-transitory computer-readable medium ofclaim 35, comprising instructions stored thereon, that if executed byone or more processors, cause the one or more processors to: based on asecond configuration that indicates a second set of one or moreparticular processing resources of the GPU restricted to performoperations for the one or more particular sources of the first command,dispatch a second command to the second set of one or more particularprocessing resources of the GPU, wherein the second set of one or moreparticular processing resources of the GPU is at least partiallydifferent than the first set of one or more particular processingresources of the GPU, and wherein the second command is provided by theone or more particular sources of the first command.
 37. Thenon-transitory computer-readable medium of claim 35, comprisinginstructions stored thereon, that if executed by one or more processors,cause the one or more processors to: after completion of the firstcommand, flush a write data buffer to a cache and invalidate state andconstant caches associated with the one or more particular processingresources that executed the first command.
 38. The non-transitorycomputer-readable medium of claim 35, comprising instructions storedthereon, that if executed by one or more processors, cause the one ormore processors to: in response to receipt of a third command from asecond source while the first command is executing: based on the firstconfiguration indicating that the second source is permitted to executea command on the one or more particular processing resources thatexecute the first command: permit the first command to completeexecution on the first set of one or more particular processingresources and allocate the third command for execution on one or moreparticular processing resources that previously executed the firstcommand and in response to completion of the third command and anunexecuted command from the one or more particular sources of the firstcommand, based on the first configuration, allocating one or more of theparticular processing resources formerly allocated to execute the thirdcommand to perform the unexecuted command from the second source. 39.The non-transitory computer-readable medium of claim 36, wherein thefirst command is associated with a compute context or a render contextand based on completion of execution of the first command, permittingaccess to the compute context or the render context for use by thesecond command.
 40. The non-transitory computer-readable medium of claim36, comprising instructions stored thereon, that if executed by one ormore processors, cause the one or more processors to: in response toreceipt of a fourth command associated with a third source, allocatingone or more of the particular processing resources to perform the fourthcommand based on the first configuration.